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authorStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-24 11:01:54 -0800
committerMartin Roth <martinroth@google.com>2016-03-10 16:55:35 +0100
commit3d840d09aea6246347afea8f19dc1d71da06aba2 (patch)
tree3490bd8e16a21f4b5e97edbe28e514573cf2c476 /src/mainboard/a-trend/atc-6240
parent422bf6b47226d68005003c17753fd30685e244c6 (diff)
northbridge/intel/i440bx: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/a-trend/atc-6240')
-rw-r--r--src/mainboard/a-trend/atc-6240/Kconfig1
-rw-r--r--src/mainboard/a-trend/atc-6240/romstage.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/a-trend/atc-6240/Kconfig b/src/mainboard/a-trend/atc-6240/Kconfig
index 6051b76010..5d0d4f6a24 100644
--- a/src/mainboard/a-trend/atc-6240/Kconfig
+++ b/src/mainboard/a-trend/atc-6240/Kconfig
@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
- select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
index 1de647e3d2..8c73824235 100644
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ b/src/mainboard/a-trend/atc-6240/romstage.c
@@ -22,7 +22,6 @@
#include <console/console.h>
#include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h>
-#include "drivers/pc80/udelay_io.c"
#include <delay.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>