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authorEric Biederman <ebiederm@xmission.com>2004-11-05 07:26:56 +0000
committerEric Biederman <ebiederm@xmission.com>2004-11-05 07:26:56 +0000
commit41d0fa38af010fdb2f9456ae3f693b1cadcc6bd6 (patch)
treedb01fb79b6e6f98999dc167567f88f40ad2d26d9 /src/mainboard/Iwill/DK8X
parent8bd555297e9c8eb8b9a006812f7a64197acff583 (diff)
- Modify all of the Opteron motherboards to have a separate logical
chip for the amdk8/root_complex git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/Iwill/DK8X')
-rw-r--r--src/mainboard/Iwill/DK8X/Config.lb85
1 files changed, 43 insertions, 42 deletions
diff --git a/src/mainboard/Iwill/DK8X/Config.lb b/src/mainboard/Iwill/DK8X/Config.lb
index 903f5c6c62..d8fc0cb5e0 100644
--- a/src/mainboard/Iwill/DK8X/Config.lb
+++ b/src/mainboard/Iwill/DK8X/Config.lb
@@ -126,54 +126,55 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
dir /pc80
config chip.h
-chip northbridge/amd/amdk8
+chip northbridge/amd/amdk8/root_complex
device pci_domain 0 on
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
- device pci 0.2 on end
- device pci 1.0 off end
+ device pci 1.0 on end
+ device pci 1.1 on end
end
- device pci 1.0 on
- chip superio/winbond/w83627thf
- device pnp 2e.0 on end
- device pnp 2e.1 on end
- device pnp 2e.2 on end
- device pnp 2e.3 on end
- device pnp 2e.4 on end
- device pnp 2e.5 on end
- device pnp 2e.6 on end
- device pnp 2e.7 on end
- device pnp 2e.8 on end
- device pnp 2e.9 on end
- device pnp 2e.a on end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627thf
+ device pnp 2e.0 on end
+ device pnp 2e.1 on end
+ device pnp 2e.2 on end
+ device pnp 2e.3 on end
+ device pnp 2e.4 on end
+ device pnp 2e.5 on end
+ device pnp 2e.6 on end
+ device pnp 2e.7 on end
+ device pnp 2e.8 on end
+ device pnp 2e.9 on end
+ device pnp 2e.a on end
+ end
end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 off end
- device pci 1.6 off end
- end
- end # LDT0
- device pci 18.0 on end # LDT1
- device pci 18.0 on end # LDT2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
-
+ end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end