- Bump the LinuxBIOS major version

- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 63 insertions, 55 deletions

diff --git a/src/mainboard/Iwill/DK8X/Config.lb b/src/mainboard/Iwill/DK8X/Config.lb
index 626eb73d2e..f95725ecbb 100644
--- a/src/mainboard/Iwill/DK8X/Config.lb
+++ b/src/mainboard/Iwill/DK8X/Config.lb
@@ -239,65 +239,73 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
 dir /pc80
 config chip.h
 
-northbridge amd/amdk8 "mc0"
-	pci 0:18.0
-	pci 0:18.0
-	pci 0:18.0
-	pci 0:18.1
-	pci 0:18.2
-	pci 0:18.3
-	southbridge amd/amd8131 "amd8131" link 0
-		pci 0:0.0
-		pci 0:0.1
-		pci 0:1.0
-		pci 0:1.1
-	end
-	southbridge amd/amd8111 "amd8111" link 0
-		pci 0:0.0
-		pci 0:1.0 on
-		pci 0:1.1 on
-		pci 0:1.2 on
-		pci 0:1.3 on
-		pci 0:1.5 off
-		pci 0:1.6 off
-		pci 1:0.0 on
-		pci 1:0.1 on
-		pci 1:0.2 on
-		pci 1:1.0 off
-		superio winbond/w83627thf link 1
-			pnp 2e.0
-			pnp 2e.1
-			pnp 2e.2
-			pnp 2e.3
-			pnp 2e.4
-			pnp 2e.5
-			pnp 2e.6
-			pnp 2e.7
-			pnp 2e.8
-			pnp 2e.9
-			pnp 2e.a
-			register "com1" = "{1, 0, 0x3f8, 4}"
-			register "lpt" = "{1}"
+chip northbridge/amd/amdk8
+	device pci_domain 0 on
+		device pci 18.0 on #  northbridge 
+			#  devices on link 0, link 0 == LDT 0 
+			chip southbridge/amd/amd8131
+				# the on/off keyword is mandatory
+				device pci 0.0 on end
+				device pci 0.1 on end
+				device pci 1.0 on end
+				device pci 1.1 on end
+			end
+			chip southbridge/amd/amd8111
+				# this "device pci 0.0" is the parent the next one
+				# PCI bridge
+				device pci 0.0 on
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 0.2 on end
+					device pci 1.0 off end
+				end
+				device pci 1.0 on
+					chip superio/winbond/w83627thf
+						device pnp 2e.0 on end
+						device pnp 2e.1 on end
+						device pnp 2e.2 on end
+						device pnp 2e.3 on end
+						device pnp 2e.4 on end
+						device pnp 2e.5 on end
+						device pnp 2e.6 on end
+						device pnp 2e.7 on end 
+						device pnp 2e.8 on end 
+						device pnp 2e.9 on end 
+						device pnp 2e.a on end 
+					end
+				end
+				device pci 1.1 on end
+				device pci 1.2 on end
+				device pci 1.3 on end 
+				device pci 1.5 off end
+				device pci 1.6 off end
+			end
+		end # LDT0
+		device pci 18.0 on end # LDT1
+		device pci 18.0 on end # LDT2
+		device pci 18.1 on end
+		device pci 18.2 on end
+		device pci 18.3 on end
+
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
 		end
 	end
 end
 
-northbridge amd/amdk8 "mc1"
-	pci 0:19.0
-	pci 0:19.0
-	pci 0:19.0
-	pci 0:19.1
-	pci 0:19.2
-	pci 0:19.3
-end
-
-cpu k8 "cpu0"
-	register "ldt0" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
-end
-
-cpu k8 "cpu1" 
-end
-
 ##
 ## Include the old serial code for those few places that still need it.
 ##