diff options
author | Ronald G. Minnich <rminnich@gmail.com> | 2004-01-27 17:08:03 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2004-01-27 17:08:03 +0000 |
commit | 22489894e189616bb5694cfed8bd951951e68fae (patch) | |
tree | cc400c06112829e06fbe5c937848278fa80df2a9 /src/mainboard/Iwill/DK8S2/failover.c | |
parent | abf9fea4a0c975f56190d061efef9ddeb6b84f81 (diff) |
will mainboards
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/Iwill/DK8S2/failover.c')
-rw-r--r-- | src/mainboard/Iwill/DK8S2/failover.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/Iwill/DK8S2/failover.c b/src/mainboard/Iwill/DK8S2/failover.c new file mode 100644 index 0000000000..bd9c17020e --- /dev/null +++ b/src/mainboard/Iwill/DK8S2/failover.c @@ -0,0 +1,42 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +static void main(void) +{ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(0); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a cpu reset? */ + if (cpu_init_detected()) { + if (last_boot_normal()) { + asm("jmp __normal_image"); + } else { + asm("jmp __cpu_reset"); + } + } + /* Is this a deliberate reset by the bios */ + else if (bios_reset_detected() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* Is this a secondary cpu? */ + else if (!boot_cpu() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + asm("jmp __normal_image"); + } +} |