diff options
| author | David W. Hendricks <dwh@lanl.gov> | 2004-05-26 17:21:02 +0000 |
|---|---|---|
| committer | David W. Hendricks <dwh@lanl.gov> | 2004-05-26 17:21:02 +0000 |
| commit | 58133c29fee609d4810bde125a2f18b4d91b72b1 (patch) | |
| tree | acbb2a01e656a92c9b1a7dd8a13b73f15b4d238f /src/mainboard/Iwill/DK8S2/auto.c | |
| parent | 36a74b0c188c866d1bcf507a61bf2808858ab858 (diff) | |
Early work on IWill DK8S2 motherboard.
Tweaking in progress.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/Iwill/DK8S2/auto.c')
| -rw-r--r-- | src/mainboard/Iwill/DK8S2/auto.c | 54 |
1 files changed, 43 insertions, 11 deletions
diff --git a/src/mainboard/Iwill/DK8S2/auto.c b/src/mainboard/Iwill/DK8S2/auto.c index 6626878668..9bc42ae64e 100644 --- a/src/mainboard/Iwill/DK8S2/auto.c +++ b/src/mainboard/Iwill/DK8S2/auto.c @@ -1,14 +1,17 @@ #define ASSEMBLY 1 #include <stdint.h> #include <device/pci_def.h> -#include <cpu/p6/apic.h> #include <arch/io.h> -#include <device/pnp.h> +#include <cpu/p6/apic.h> +#include <device/pnp_def.h> #include <arch/romcc_io.h> +#include <arch/smp/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/early_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/k8/apic_timer.c" @@ -17,8 +20,26 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#define SIO_BASE 0x2e +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void hard_reset(void) +{ + set_bios_reset(); + + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); + } + + static void soft_reset(void) + { + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + } + static void memreset_setup(void) { @@ -102,6 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" +#if 0 static void enable_lapic(void) { @@ -154,6 +176,7 @@ static void pc87360_enable_serial(void) pnp_set_enable(SIO_BASE, 1); pnp_set_iobase0(SIO_BASE, 0x3f8); } +#endif #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -188,22 +211,31 @@ static void main(void) }, #endif }; + int needs_reset; + + enable_lapic(); + init_timer(); + if (cpu_init_detected()) { asm("jmp __cpu_reset"); } - enable_lapic(); - init_timer(); + + distinguish_cpu_resets(); if (!boot_cpu()) { stop_this_cpu(); } - pc87360_enable_serial(); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); - + needs_reset = setup_coherent_ht_domain(); + needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + #if 0 print_pci_devices(); #endif |