diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 04:59:03 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:08 +0000 |
| commit | df7de392ef5f8e1654df96a1a050820eb3779012 (patch) | |
| tree | 341c3b10cc90f3831a9aadbb90d50d4edb0b47f4 /src/mainboard/51nb | |
| parent | dcddc53fde2d559beef998d3c17e9b7a227e3665 (diff) | |
skl mainboards/dt: Move SATA related settings into SATA device scope
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/51nb')
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 7a77e64792..1f2fa40dee 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -30,15 +30,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "1" - - # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -106,7 +97,21 @@ chip soc/intel/skylake end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp9 on end |