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| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-12-12 22:42:41 +0000 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-12-17 20:05:49 +0000 |
| commit | ac857ca3b166d385caa4faf62b4f1b8fc3b3f2da (patch) | |
| tree | 7dadb9454b084736d7a931b8cb98c5da5dfe11db /src/mainboard/51nb | |
| parent | a04400d1aac35299568774304cf9664188570d07 (diff) | |
soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
coreboot already unconditionally enables CLKRUN_EN in SoC common code.
Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.
Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/51nb')
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 43f272e5a8..b51c73c486 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -56,8 +56,6 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "PmConfigPciClockRun" = "1" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" |