diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-04-30 00:44:04 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-04 18:52:17 +0000 |
| commit | 13dee2a9113bfbcce9ae8b302a759af062ecf486 (patch) | |
| tree | 85f1e4c7cfa1357e8200c87f7d2390de25cab6ee /src/mainboard/51nb | |
| parent | e01054d86eecfff846764e640eaafe58b5d5fb5d (diff) | |
soc/intel/skl: always enable SataPwrOptEnable
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization
Registers) when SataPwrOptEnable=0, which currently is the default in
coreboot and FSP. Even if FSP's default was 1, coreboot would reset it.
This can lead to all sorts of problems and errors, for example:
- links get lost
- only 1.5 or 3 Gbps instead of 6 Gbps
- "unaligned write" errors in Linux
- ...
At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and
purism/librem13v2) SATA is not working correctly and showing such
symptoms.
To let FSP correctly initialize the SATA controller, enable the option
SataPwrOptEnable statically. There is no valid reason to disable it,
which might break SATA, anyway.
Currently, there are no reported issues on CML and CNL, so a change
there could not be tested reliably. SKL/KBL was tested successfully
without any noticable downsides. Thus, only SKL gets changed for now.
Change-Id: I8531ba9743453a3118b389565517eb769b5e7929
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/51nb')
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 82bbb1fc74..e453aa432f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -48,7 +48,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "SataPwrOptEnable" = "1" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" |