mb/51nb: Add support for the 51nb X210

The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:

* EC firmware is contained within the system SPI flash, and so a blob of
  EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
  GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
  configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different

All hardware appears to work as expected, although the SD reader is
untested.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 34 insertions, 0 deletions

diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl
new file mode 100644
index 0000000000..441a80dd4a
--- /dev/null
+++ b/src/mainboard/51nb/x210/dsdt.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	Name(\DSEN, 1)
+
+	#include "acpi/platform.asl"
+
+	#include <soc/intel/skylake/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+		#include "acpi/graphics.asl"
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
+}