diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 03:39:24 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:02 +0000 |
| commit | dcddc53fde2d559beef998d3c17e9b7a227e3665 (patch) | |
| tree | f3061a3764892f73bc5dd827134a795c275b685f /src/mainboard/51nb/x210/devicetree.cb | |
| parent | 6c83a71b0a803c922b02b613e927d4c49b944c32 (diff) | |
skl mainboards/dt: Move genx_dec settings into LPC device scope
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/51nb/x210/devicetree.cb')
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 51cb89ad29..7a77e64792 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -26,9 +26,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" - # Disable DPTF register "dptf_enable" = "0" @@ -114,6 +111,9 @@ chip soc/intel/skylake device ref pcie_rp4 on end device ref pcie_rp9 on end device ref lpc_espi on + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + chip ec/51nb/npce985la0dx device pnp 0c09.0 on end device pnp 4e.5 on end |