mb/51nb: Add support for the 51nb X210

The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:

* EC firmware is contained within the system SPI flash, and so a blob of
  EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
  GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
  configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different

All hardware appears to work as expected, although the SD reader is
untested.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

6 files changed, 351 insertions, 0 deletions

diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl
new file mode 100644
index 0000000000..9064ad5cee
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/battery.asl
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Device (BAT)
+{
+	Name (_HID, EisaId ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Method (_STA, 0, NotSerialized)  // _STA: Status
+	{
+		If (B1SS)
+		{
+			Return (0x1F)
+		}
+		Else
+		{
+			Return (0x0F)
+		}
+	}
+
+	Name (PBIF, Package () {
+		0x00000001,  /* 0x00: Power Unit: mAH */
+		0xFFFFFFFF,  /* 0x01: Design Capacity */
+		0xFFFFFFFF,  /* 0x02: Last Full Charge Capacity */
+		0x00000001,  /* 0x03: Battery Technology: Rechargeable */
+		0xFFFFFFFF,  /* 0x04: Design Voltage */
+		0x00000000,  /* 0x05: Design Capacity of Warning */
+		0xFFFFFFFF,  /* 0x06: Design Capacity of Low */
+		0x00000001,  /* 0x07: Capacity Granularity 1 */
+		0x00000001,  /* 0x08: Capacity Granularity 2 */
+		"Y91",       /* 0x09: Model Number */
+		"",          /* 0x0a: Serial Number */
+		"LION",      /* 0x0b: Battery Type */
+		"CJOYIN"     /* 0x0c: OEM Information */
+	})
+
+	Method (_BIF, 0, Serialized)
+	{
+		/* Design Capacity */
+		Store (DGCP, Index (PBIF, 1))
+
+		/* Last Full Charge Capacity */
+		Store (FLCP, Index (PBIF, 2))
+
+		/* Design Voltage */
+		Store (DGVO, Index (PBIF, 4))
+
+		/* Design Capacity of Warning */
+		Store (BDW, Index (PBIF, 5))
+
+		/* Design Capacity of Low */
+		Store (BDL, Index (PBIF, 6))
+
+		Return (PBIF)
+	}
+
+	Name (PBST, Package () {
+		0x00000000,  /* 0x00: Battery State */
+		0xFFFFFFFF,  /* 0x01: Battery Present Rate */
+		0xFFFFFFFF,  /* 0x02: Battery Remaining Capacity */
+		0xFFFFFFFF,  /* 0x03: Battery Present Voltage */
+	})
+
+	Method (_BST, 0, NotSerialized)  // _BST: Battery Status
+	{
+		/*
+		* 0: BATTERY STATE
+		*
+		* bit 0 = discharging
+		* bit 1 = charging
+		* bit 2 = critical level
+		*/
+		Store (BSTS, Index (PBST, 0))
+
+		/*
+		* 1: BATTERY PRESENT RATE
+		*/
+		Store (BPR, Index (PBST, 1))
+
+		/*
+		* 2: BATTERY REMAINING CAPACITY
+		*/
+		Store (BRC, Index (PBST, 2))
+
+		/*
+		* 3: BATTERY PRESENT VOLTAGE
+		*/
+		Store (BPV, Index (PBST, 3))
+
+		Return (PBST)
+	}
+}
diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl
new file mode 100644
index 0000000000..5ebc0aca4c
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/ec.asl
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Device (EC)
+{
+	Name (_HID, EisaId ("PNP0C09"))
+	Name (_UID, 0)
+
+	Name (_GPE, 0x4F)  // _GPE: General Purpose Events
+	Name (_CRS, ResourceTemplate () {
+		IO (Decode16, 0x62, 0x62, 1, 1)
+		IO (Decode16, 0x66, 0x66, 1, 1)
+	})
+
+	OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x50),
+		CTMP,   8,
+		CFAN,   8,
+		B1SS,   1,
+		BSTS,   2,
+		ACIN,   1,
+		Offset (0x53),
+		BKLG,   8,
+		TOUP,   1,
+		WIRE,   1,
+		BLTH,   1,
+		LIDC,   1,
+		APFG,   1,
+		WRST,   1,
+		BTST,   1,
+		ACEB,   1,
+		CAME,   1,
+		Offset (0x60),
+		DGCP,   16,
+		FLCP,   16,
+		DGVO,   16,
+		BDW,    16,
+		BDL,    16,
+		BPR,    16,
+		BRC,    16,
+		BPV,    16
+	}
+
+	Method (_REG, 2, NotSerialized)
+	{
+		/* Initialize AC power state */
+		Store (ACIN, \PWRS)
+
+		/* Initialize LID switch state */
+		Store (LIDC, \LIDS)
+	}
+
+	/* KEY_BRIGHTNESSUP */
+	Method (_Q04)
+	{
+		Notify(\_SB.PCI0.GFX0.LCD, 0x86)
+	}
+
+	/* KEY_BRIGHTNESSDOWN */
+	Method (_Q05)
+	{
+		Notify(\_SB.PCI0.GFX0.LCD, 0x87)
+	}
+
+	/* Battery Information Event */
+	Method (_Q0C)
+	{
+		Notify (BAT, 0x81)
+	}
+
+	/* AC event */
+	Method (_Q0D)
+	{
+		Store (ACIN, \PWRS)
+		Notify (AC, 0x80)
+	}
+
+	/* Lid event */
+	Method (_Q0E)
+	{
+		Store (LIDC, \LIDS)
+		Notify (LID0, 0x80)
+	}
+
+	/* Battery Information Event */
+	Method (_Q13)
+	{
+		Notify (BAT, 0x81)
+	}
+
+	/* Battery Status Event */
+	Method (_Q14)
+	{
+		Notify (BAT, 0x80)
+	}
+
+	Device (AC)
+	{
+		Name (_HID, "ACPI0003")
+		Name (_PCL, Package () { \_SB })
+
+		Method (_STA)
+		{
+			Return (0x0F)
+		}
+		Method (_PSR)
+		{
+			Return (\PWRS)
+		}
+	}
+
+	#include "battery.asl"
+}
diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl
new file mode 100644
index 0000000000..218b95758f
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/graphics.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+	Method (_DOS, 1, NotSerialized)
+	{
+		/* We never do anything in firmware, so _DOS is a noop */
+	}
+	Method (_DOD, 0, NotSerialized)
+	{
+		return (Package (0x03)
+		{
+			0x80000410, /* LCD */
+			0x80000120, /* VGA */
+			0x80000330 /* DP */
+		})
+	}
+	Device (LCD)
+	{
+		Method (_ADR, 0, Serialized)
+		{
+			Return (0x800000410)
+		}
+
+		Method (_BCL, 0, NotSerialized)
+		{
+			Return (Package (0x12)
+			{
+				0x0A,
+				0x0F,
+				0x00,
+				0x01,
+				0x02,
+				0x03,
+				0x04,
+				0x05,
+				0x06,
+				0x07,
+				0x08,
+				0x09,
+				0x0A,
+				0x0B,
+				0x0C,
+				0x0D,
+				0x0E,
+				0x0F
+			})
+		}
+		Method (_BCM, 1, NotSerialized)
+		{
+			\_SB.PCI0.LPCB.EC.BKLG = Arg0
+		}
+		Method (_BQC, 0, NotSerialized)
+		{
+			Return (\_SB.PCI0.LPCB.EC.BKLG)
+		}
+	}
+}
diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl
new file mode 100644
index 0000000000..fb389a40ad
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/mainboard.asl
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+
+		Method (_LID)
+		{
+			Return (\LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+
+		Name (_PRW, Package () { 27, 4 })
+	}
+
+	Device (SLPB)
+	{
+		Name (_HID, EisaId ("PNP0C0E"))
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl
new file mode 100644
index 0000000000..d0e34b6254
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/platform.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS)
+	Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS)
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl
new file mode 100644
index 0000000000..cb77a3c7a8
--- /dev/null
+++ b/src/mainboard/51nb/x210/acpi/superio.asl
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <drivers/pc80/pc/ps2_controller.asl>