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authorAshish Kumar Mishra <ashish.k.mishra@intel.com>2024-03-25 22:17:30 +0530
committerSubrata Banik <subratabanik@google.com>2024-03-28 07:26:45 +0000
commite6893677c1ca4d15342e2201b877d54d015a01b1 (patch)
treea3ceccca2a8be49135267821399e3c50c49b2de2 /src/lib
parent3ee97e47a6b814df58584031c8412ae1960360b9 (diff)
lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
For dram_type 21 the switch case in use_ddr4_params function falls to default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block for dram_type 21 in the function. With this patch below NOTE will not be observed in the log: [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params BUG=None BRANCH=None TEST=Boot brox SKU1/SKU2 and verify logs for default case Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/lib')
-rw-r--r--src/lib/spd_bin.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index e005ccbad9..01f451da65 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -35,6 +35,7 @@ static bool use_ddr4_params(int dram_type)
case SPD_DRAM_DDR4:
case SPD_DRAM_DDR5:
case SPD_DRAM_LPDDR5:
+ case SPD_DRAM_LPDDR5X:
case SPD_DRAM_LPDDR4:
case SPD_DRAM_LPDDR4X:
return true;