soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes

Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.

- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
  it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
  SPMI kernel driver.

TEST=GPU bringup correctly.
BUG=b:233720142

Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>

0 files changed, 0 insertions, 0 deletions