diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-04-09 14:03:37 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 21:20:26 +0000 |
| commit | 570c654db777bd59714150de1684815c53d83e22 (patch) | |
| tree | 8cdefd9f83f1cee29fcc47c0d8f349c5afb3e0a4 /src/lib | |
| parent | 74d14b8ff71c8c80ccdf4eaa6cd0b16e4821da54 (diff) | |
lib/espi_debug: Add espi_show_slave_peripheral_channel_configuration
Prints out the following:
eSPI Slave Peripheral configuration:
Peripheral Channel Maximum Read Request Size: 64 bytes
Peripheral Channel Maximum Payload Size Selected: 64 bytes
Peripheral Channel Maximum Payload Size Supported: 64 bytes
Bus master: disabled
Peripheral Channel: ready
Peripheral Channel: enabled
BUG=none
TEST=boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7d598ee4f0f9d8ec0b37767e6a5a70288be2cb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/espi_debug.c | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/src/lib/espi_debug.c b/src/lib/espi_debug.c index 1ddcb40baa..6087283ffd 100644 --- a/src/lib/espi_debug.c +++ b/src/lib/espi_debug.c @@ -115,3 +115,89 @@ void espi_show_slave_general_configuration(uint32_t config) printk(BIOS_DEBUG, " Flash Access Channel supported\n"); printk(BIOS_DEBUG, "\n"); } + +void espi_show_slave_peripheral_channel_configuration(uint32_t config) +{ + uint32_t request_size; + uint32_t payload_size; + + printk(BIOS_DEBUG, "eSPI Slave Peripheral configuration:\n"); + + printk(BIOS_DEBUG, " Peripheral Channel Maximum Read Request Size: "); + request_size = config & ESPI_SLAVE_PERIPH_MAX_READ_SIZE_MASK; + switch (request_size) { + case ESPI_SLAVE_PERIPH_MAX_READ_64B: + printk(BIOS_DEBUG, "64 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_READ_128B: + printk(BIOS_DEBUG, "128 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_READ_256B: + printk(BIOS_DEBUG, "256 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_READ_512B: + printk(BIOS_DEBUG, "512 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_READ_1024B: + printk(BIOS_DEBUG, "1024 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_READ_2048B: + printk(BIOS_DEBUG, "2048 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_READ_4096B: + printk(BIOS_DEBUG, "4096 bytes\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown\n"); + } + + printk(BIOS_DEBUG, " Peripheral Channel Maximum Payload Size Selected: "); + payload_size = config & ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_MASK; + switch (payload_size) { + case ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_64B: + printk(BIOS_DEBUG, "64 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_128B: + printk(BIOS_DEBUG, "128 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_256B: + printk(BIOS_DEBUG, "256 bytes\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown\n"); + } + + printk(BIOS_DEBUG, " Peripheral Channel Maximum Payload Size Supported: "); + payload_size = config & ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_MASK; + switch (payload_size) { + case ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_64B: + printk(BIOS_DEBUG, "64 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_128B: + printk(BIOS_DEBUG, "128 bytes\n"); + break; + case ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_256B: + printk(BIOS_DEBUG, "256 bytes\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown\n"); + } + + printk(BIOS_DEBUG, " Bus master: "); + if (config & ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE) + printk(BIOS_DEBUG, "enabled\n"); + else + printk(BIOS_DEBUG, "disabled\n"); + + printk(BIOS_DEBUG, " Peripheral Channel: "); + if (config & ESPI_SLAVE_CHANNEL_READY) + printk(BIOS_DEBUG, "ready\n"); + else + printk(BIOS_DEBUG, "not ready\n"); + + printk(BIOS_DEBUG, " Peripheral Channel: "); + if (config & ESPI_SLAVE_CHANNEL_ENABLE) + printk(BIOS_DEBUG, "enabled\n"); + else + printk(BIOS_DEBUG, "disabled\n"); +} |