diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2020-11-30 14:30:15 -0600 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-14 08:23:41 +0000 |
| commit | 8ead1dc8752b4cc7979792295940d973714394ac (patch) | |
| tree | b92fb91c3c9517fc602b7765e5f7228869286ba2 /src/lib | |
| parent | 92106b166671a315a2b1e8f5cc467f2fa0823301 (diff) | |
src/lib: Add Kconfig option for SPD cache in FMAP
Currently, the option to cache DIMM SPD data in an FMAP region
is closely coupled to a single board (google/hatch) and requires
a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds
a correctly sized and aligned RW_SPD_CACHE region to the default FMAP.
Add a Kconfig option for the region name, replacing the existing hard-
coded instance in spd_cache.h. Change the inclusion of spd_cache.c to
use this new Kconfig, rather than the board-specific one currently used.
Lastly, have google/hatch select the new Kconfig when appropriate to
ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify
FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Also tested on an out-of-tree Purism board.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/Kconfig | 17 | ||||
| -rw-r--r-- | src/lib/Makefile.inc | 2 |
2 files changed, 18 insertions, 1 deletions
diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 168a06801a..e1d56fe26b 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -46,6 +46,23 @@ config DIMM_SPD_SIZE config SPD_READ_BY_WORD bool +config SPD_CACHE_IN_FMAP + bool + default n + help + Enables capability to cache DIMM SPDs in a dedicated FMAP region + to speed loading of SPD data. Currently requires board-level + romstage implementation to read/write/utilize cached SPD data. + When the default FMAP is used, will create a region named RW_SPD_CACHE + to store the cached SPD data. + +config SPD_CACHE_FMAP_NAME + string + depends on SPD_CACHE_IN_FMAP + default "RW_SPD_CACHE" + help + Name of the FMAP region created in the default FMAP to cache SPD data. + if RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 07555a7b03..8424cbfac3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -372,4 +372,4 @@ endif ramstage-y += uuid.c -romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c +romstage-$(CONFIG_SPD_CACHE_IN_FMAP) += spd_cache.c |