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authorShelley Chen <shchen@google.com>2020-09-29 10:05:00 -0700
committerShelley Chen <shchen@google.com>2020-10-02 23:11:16 +0000
commit156bc6f47a7c4536649f79ee037c7eed063d1805 (patch)
tree89a809497eaa0eeca3d3c71ceda5c368ea72897e /src/lib
parent6c2568f4f58b9a1b209c9af36d7f980fde784f08 (diff)
soc/intel/braswell: Increase dcache size
Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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