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authorAaron Durbin <adurbin@chromium.org>2013-03-26 13:09:39 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-29 20:09:36 +0100
commitbc07f5d93552640793254ce003937ec646120a21 (patch)
tree091f2189c38629d64579c5864220f8b2f2039db0 /src/lib
parentf567f16af4c3cbfcadc3bc5c44b569a592829262 (diff)
x86: add rom cache variable MTRR index to tables
Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the coreboot tables. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/lib')
-rw-r--r--src/lib/coreboot_table.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index b9a82a831d..765c51001e 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -40,6 +40,9 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
+#if CONFIG_ARCH_X86
+#include <cpu/x86/mtrr.h>
+#endif
static struct lb_header *lb_table_init(unsigned long addr)
{
@@ -237,6 +240,24 @@ static inline void lb_vboot_handoff(struct lb_header *header) {}
#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
#endif /* CONFIG_CHROMEOS */
+static void lb_x86_rom_cache(struct lb_header *header)
+{
+#if CONFIG_ARCH_X86
+ long mtrr_index;
+ struct lb_x86_rom_mtrr *lb_x86_rom_mtrr;
+
+ mtrr_index = x86_mtrr_rom_cache_var_index();
+
+ if (mtrr_index < 0)
+ return;
+
+ lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header);
+ lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR;
+ lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr);
+ lb_x86_rom_mtrr->index = mtrr_index;
+#endif
+}
+
static void add_cbmem_pointers(struct lb_header *header)
{
/*
@@ -539,6 +560,8 @@ unsigned long write_coreboot_table(
lb_strings(head);
/* Record our framebuffer */
lb_framebuffer(head);
+ /* Communicate x86 variable MTRR ROM cache information. */
+ lb_x86_rom_cache(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */