diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-05 19:46:45 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-25 00:57:35 +0100 |
| commit | 4337020b950454815204eed4e43a894be0b125ca (patch) | |
| tree | 7aa3a4ad420a54b3079f3216d577aafab1bca2e0 /src/lib | |
| parent | 20f83d56561879045ecade24d51e79dfb151baf6 (diff) | |
Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.
CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency
Remove this as a buggy feature until we figure out how to do it properly
if necessary.
Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/coreboot_table.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14cc81..904185ab75 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ |