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authorLijian Zhao <lijian.zhao@intel.com>2017-09-25 23:58:39 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-27 16:02:49 +0000
commitf7bcc180eb5aa297aa3e8ff9a3968414a238395a (patch)
tree0ca8288b2a857866c659edece739e6d03e69e297 /src/lib/wrdd.c
parent33803aa04adfece6b7d576e2b2702d2131952928 (diff)
soc/intel/common: Add Cannonlake PCI id
Add extra pci ids of CNLU and CNLY into common code. Change-Id: Ibbf3d500a780cc6a758fda1ddbec2b9953fb5a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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