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authorSathyanarayana Nujella <sathyanarayana.nujella@intel.com>2016-10-31 10:48:43 -0700
committerMartin Roth <martinroth@google.com>2016-11-07 20:15:13 +0100
commit50198c117839ee01c331a827dc57b6293c989f34 (patch)
treeda689ef8b42bc4e4449ac980d9c4e2fbb4e5d7e7 /src/lib/tpm2_marshaling.c
parent37742f6870ec1d4b860769db25ef665cdb7c1615 (diff)
mainboard/google/reef: update DMIC related pins configuration
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record on other potential DMIC's. DMIC blobs configure the clocks. For stereo & quad channel record, both CLK_A1 and CLK_B1 are enabled. For mono channel record, only CLK_A1 is enabled. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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