diff options
| author | ZhengShunQian <zhengsq@rock-chips.com> | 2016-10-28 15:58:51 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-11-03 13:53:31 +0100 |
| commit | 8859afdb44194cacf0bc1c694b09eb94d568dab9 (patch) | |
| tree | 19c884aa3db008598afa66bb5c6b741d5e45d94c /src/lib/tlcl_structures.h | |
| parent | 60687b52076ec6d4da3587859adcb0d49a05aca0 (diff) | |
google/veyron*: add DDR configs for new samsung DDR
Add the new samsung DDR configs for all veyron except veyron_rialto:
* K4E6E304EB-EGCE, ramid = 0010, 4GB
* K4E8E324EB-EGCF, ramid = 1100, 2GB
BRANCH=veyron
BUG=none
TEST=boot fievel board
Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c
Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345748
Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7)
Original-Reviewed-on: https://chromium-review.googlesource.com/404690
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/lib/tlcl_structures.h')
0 files changed, 0 insertions, 0 deletions