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authorLin Huang <hl@rock-chips.com>2017-11-16 09:52:27 +0800
committerJulius Werner <jwerner@chromium.org>2017-11-28 19:14:25 +0000
commitecd600a0caa18b0346e4b8024aae2263db0d7821 (patch)
tree225ac9e80b1f21e1609e303557a2553321f485a9 /src/lib/tlcl.c
parent5220e5fba6606224976e8a540c7a07d447d8b3d8 (diff)
rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide
Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/lib/tlcl.c')
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