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authorShelley Chen <shchen@google.com>2024-01-07 23:01:38 -0800
committerShelley Chen <shchen@google.com>2024-01-09 07:50:33 +0000
commit3738e7408d6b12fcc4e29aeda5973e632198a344 (patch)
treea1535a7ba60f45efa5c04f99ef16c1babe22f533 /src/lib/timer.c
parent0acae97863cb842a8a6a56cb0290596510910a8b (diff)
mb/google/brox: Fix error in DDR DQS config
The DQS mapping for DIMM idx 6 was discovered to be incorrect to what was in the schematics. Correcting the mistake in this CL. BUG=b:311450057,b:300690448 BRANCH=None TEST=tested on device and it passed memory training Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/lib/timer.c')
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