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authorSubrata Banik <subratabanik@google.com>2022-04-14 13:48:53 +0530
committerSubrata Banik <subratabanik@google.com>2022-04-23 17:16:15 +0000
commit4c6072130c0979095a6639af4c5c06937f785145 (patch)
tree67783eed8d484767c39f54aceaf8d97226783c71 /src/lib/thread.c
parentfa2854d3dc6d5a56f465e6aef4621503ca5f5e34 (diff)
soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
This patch implements a helper function to perform LPC registers lock down configuration. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified LPC PCI configuration register offset 0xDC bits BILD and LE are set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/lib/thread.c')
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