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authorHung-Te Lin <hungte@chromium.org>2013-06-26 20:22:50 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 23:17:16 +0200
commitcab3621446542fadf67e9406c4ae39fb63a0536f (patch)
tree49e7d7453f4dea3791e1280f672de9a73b0a3929 /src/lib/thread.c
parented1742cafec5627023e12f8bde52282247d17ddd (diff)
armv7/exynos5420: Revise SPI open/close/reset procedure.
The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/lib/thread.c')
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