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authorFrank Wu <frank_wu@compal.corp-partner.google.com>2022-12-14 10:03:50 +0800
committerKarthik Ramasubramanian <kramasub@google.com>2022-12-15 14:28:02 +0000
commit3a4e201a21551acae101a5b87e771b01421dc785 (patch)
tree8328fc28c72c50e6155dd7bc9453cdcd97e3d9ff /src/lib/string.c
parent315d3264b603e16f5694ac0b61b139f18409e51e (diff)
spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD. Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E. BUG=b:261530632 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/lib/string.c')
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