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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-11-28 09:21:58 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-29 12:17:32 +0000
commit1a5ce95815210032783d01e830390ee5b6a54dc5 (patch)
tree2355cc04a346d505bda93f8fa316e79cde858e38 /src/lib/rmodule.ld
parenta94a153477584ba2d168021f23fa571f048e6767 (diff)
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29882 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib/rmodule.ld')
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