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authorMartin Roth <martinroth@google.com>2015-12-22 12:40:53 -0700
committerMartin Roth <martinroth@google.com>2016-01-08 02:44:15 +0100
commitb95a0745865a084e5426b9930eba0dadd3301c23 (patch)
tree609e6d1fe06b12c9e6b4896612ebcc72261dc6f3 /src/lib/memrange.c
parent481a19cf99a9736c089320df33d3248522e0efc9 (diff)
fsp_baytrail: Add additional PCI space above 4GB
This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
Diffstat (limited to 'src/lib/memrange.c')
0 files changed, 0 insertions, 0 deletions