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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-11-09 08:54:35 +0100
committerWerner Zeh <werner.zeh@siemens.com>2018-11-12 07:26:46 +0000
commitc27ce827dc788e2c34d72fcc43097d8e858e2f9f (patch)
treeed2f9455b209f3bfca16bc4ca39397e2fe9ba379 /src/lib/memmove.c
parent4946804f0b6536df3e7a46654c0dbbc3172b1de8 (diff)
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/lib/memmove.c')
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