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| author | Furquan Shaikh <furquan@google.com> | 2020-07-29 00:44:25 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-30 15:58:28 +0000 |
| commit | 27c9762f95da4c16721245daf60f924aa066adae (patch) | |
| tree | d162f71b1fafb3ca230a6f2043e16bd8bd66cea0 /src/lib/malloc.c | |
| parent | 23ade0ee150fd7e3dcd44d5ab265bc2403b321c2 (diff) | |
soc/amd/picasso: Split ops for internal and external PCIe GPP bridges
This change splits the device operations for internal and external PCIe
GPP bridges so that the external bridges use `pciexp_scan_bridge()`
instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for
external GPP bridges to enable ASPM on downstream devices if supported.
BUG=b:162352484
TEST=Verified on Trembyle:
$ lspci -s 1:00.0 -vvv | grep ASPM
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/lib/malloc.c')
0 files changed, 0 insertions, 0 deletions