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author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-02-05 19:40:01 +0530 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-09 14:20:21 +0000 |
commit | b25261fc7ffdb1a98ffa7a9f6d16f3b51ef64b67 (patch) | |
tree | bbea29b8f204d9d047c3e56a206fa093c0b94786 /src/lib/libgcov.c | |
parent | 9b5b17feca7d970879230e35941645abf7ff926c (diff) |
mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61586
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib/libgcov.c')
0 files changed, 0 insertions, 0 deletions