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authorV Sowmya <v.sowmya@intel.com>2020-11-30 19:49:16 +0530
committerPaul Fagerburg <pfagerburg@chromium.org>2020-12-01 15:27:01 +0000
commita99f61fec41f22c6c518d53078c322ca9891884c (patch)
tree131c88e91501f8c62618a492a2790b1a30aed3df /src/lib/libgcc.c
parente2ce56928c11417114906a1dae2b12a3977bd39e (diff)
mb/intel/jslrvp: Modify the flash layout for fsp debug build
Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/lib/libgcc.c')
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