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authorRaul E Rangel <rrangel@chromium.org>2022-02-24 11:49:52 -0700
committerRaul Rangel <rrangel@chromium.org>2022-02-26 00:09:27 +0000
commit737ad67d122b24f8309ad76b66b5d7a26873eb39 (patch)
treedc69a78aedbd7f78e96d6688c29582ce1eb40f78 /src/lib/imd_cbmem.c
parent5e0ed5016c8096a58b3d8758495c0969e0c1052c (diff)
soc/amd/common/psp_verstage: Add missing post codes on S0i3 resume
We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/lib/imd_cbmem.c')
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