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| author | Wim Vervoorn <wvervoorn@eltan.com> | 2019-12-13 12:06:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-17 13:11:09 +0000 |
| commit | d908916642eadf613e02d083cc54c9dacea28152 (patch) | |
| tree | 3a373bcf02bc3c85dcd967342c318cd45c59d77a /src/lib/gpio.c | |
| parent | 9cb88a70f7a636806752542216e177ba625e77d2 (diff) | |
soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range
The base address of the 16 MB flash range was reported as 0xFFF00000
this causes the range to extend above the 4GB boundary.
Change the base to 0xFF000000 as is the case with e.g. Skylake.
BUG=N/A
TEST=build
Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/lib/gpio.c')
0 files changed, 0 insertions, 0 deletions