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authorLee Leahy <leroy.p.leahy@intel.com>2014-11-20 16:56:44 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-04 12:40:30 +0200
commit4a69c34d54d587ba00c6c8e4f9056596014a7541 (patch)
tree999e9f145ca9d35c50e8bcd2823b673c5ec4bc3d /src/lib/gcov-iov.h
parent9f5a5c532343fe72753fc507b0f2ef1a26afabd3 (diff)
Broadwell: Pass TSC value to romstage_main
The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9280 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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