PCIe : Adding some error/not-null condition checking

This patch checks for following conditions
(1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found
    then don't enable LTR.
(2)
    2.1) set_L1_ss_latency is member if ops_pci, which could be NULL.
	 so confirm ops_pci is not NULL before calling its member function.
    2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency.

BUG=none
BRANCH=none
TEST=build and boot coreboot with L1 substate enabled on sklrvp3.

Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181
Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/10559
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

0 files changed, 0 insertions, 0 deletions