diff options
| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-20 01:39:20 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:36 +0200 |
| commit | 074a028ef715763ecda99386d472c751092150a1 (patch) | |
| tree | 3901c0a1a18f31ecf520060449cb1edfee4d3d52 /src/lib/coreboot_table.c | |
| parent | f6d7baa8fa31a87e4a6f47fc3da82fc093f114a3 (diff) | |
Samus: Synchronization with FRC to enable PCIe Relaxed Order.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324
Original-BUG=None
Original-TEST=Modify settings, build and update the image to Samus and
Original-check the settings are applied to Registers.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
Original-Reviewed-on: https://chromium-review.googlesource.com/219073
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31
Reviewed-on: http://review.coreboot.org/9206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/lib/coreboot_table.c')
0 files changed, 0 insertions, 0 deletions