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authorMichał Żygowski <michal.zygowski@3mdeb.com>2023-03-22 11:07:22 +0100
committerMichał Żygowski <michal.zygowski@3mdeb.com>2023-03-23 08:46:34 +0000
commit14701a4df3cd40fe1eb817e8a1b3bfa064e7f7c1 (patch)
tree998826488d1798e075f3bba9a9d91b4f0301a9f6 /src/lib/cbmem_common.c
parent496e4e95c4cba9f5414cd8137fa151a9b3fe0b21 (diff)
soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC Kconfig
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib/cbmem_common.c')
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