1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c

2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)

3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.

4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.

I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 29 insertions, 4 deletions

diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 5490a1fef6..d85c748810 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -36,11 +36,32 @@ struct cbmem_entry {
 	u64 size;
 } __attribute__((packed));
 
-#ifndef __PRE_RAM__
-struct cbmem_entry *bss_cbmem_toc;
-#define get_cbmem_toc()	bss_cbmem_toc
+
+#ifdef __PRE_RAM__
+
+/* note this should be done as weak function but we do #include
+   of C files in the romstage breaking this (in same compile
+   unit is weak and non weak function
+struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
+*/
+#ifndef get_cbmem_toc
+	#define get_cbmem_toc()	(struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE)
+#endif
+
 #else
-#define get_cbmem_toc()	(struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE)
+
+static struct cbmem_entry *bss_cbmem_toc;
+
+struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
+{
+	return bss_cbmem_toc;
+}
+
+void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x)
+{
+	/* do nothing, this should be called by chipset to save TOC in NVRAM */
+}
+
 #endif
 
 /**
@@ -70,6 +91,10 @@ void cbmem_init(u64 baseaddr, u64 size)
 		for (;;) ;
 	}
 
+	/* we don't need to call this in romstage, usefull only from ramstage */
+#ifndef __PRE_RAM__
+	set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr);
+#endif
 	memset(cbmem_toc, 0, CBMEM_TOC_RESERVED);
 
 	cbmem_toc[0] = (struct cbmem_entry) {