diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2019-11-04 20:49:10 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-02 12:04:38 +0000 |
| commit | fdcc9ab317af2ae9cd69cb2490d3a4444180429a (patch) | |
| tree | e8ffba4d330aa12dd1dab94408e15bc871fcc76b /src/include | |
| parent | c9b13594eb8d425e54a126b5c10e3f6fbc41528b (diff) | |
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips.
According to doc #605546:
CML-S (6+2) G0: A0650h
CML-S (6+2) G1: A0653h
CML-S (10+2, 8+2) P0: A0651h
CML-S (6+2, 10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh
CMP-H WM490: 068Eh
CMP-H QM480: 068Ch
CMP-H H470: 0684h
CMP-H Z490: 0685h
CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0f96737f3b..b75e596d19 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2769,6 +2769,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470 0x068D +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490 0x068E +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480 0x068C +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480 0x0697 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470 0x0684 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490 0x0685 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470 0x0687 +#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_0 0xA080 #define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI 0xA081 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI 0xA082 @@ -3262,6 +3270,14 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0 0x9BC8 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x3E9B +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 #define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 @@ -3313,7 +3329,9 @@ #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 #define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 #define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 |