smbios: Add memory type 9 system slot support

Add SMBIOS type 9 system slots into coreboot, the definiation is up to
date with SMBIOS spec 3.2

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 150 insertions, 0 deletions

diff --git a/src/include/smbios.h b/src/include/smbios.h
index 5e069470e1..afe77d6ad9 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -26,6 +26,16 @@ int smbios_add_string(u8 *start, const char *str);
 int smbios_string_table_len(u8 *start);
 
 /* Used by mainboard to add an on-board device */
+enum misc_slot_type;
+enum misc_slot_length;
+enum misc_slot_usage;
+enum slot_data_bus_bandwidth;
+int smbios_write_type9(unsigned long *current, int *handle,
+			const char *name, const enum misc_slot_type type,
+			const enum slot_data_bus_bandwidth bandwidth,
+			const enum misc_slot_usage usage,
+			const enum misc_slot_length length,
+			u8 slot_char1, u8 slot_char2, u8 bus, u8 dev_func);
 enum smbios_bmc_interface_type;
 int smbios_write_type38(unsigned long *current, int *handle,
 			const enum smbios_bmc_interface_type interface_type,
@@ -481,6 +491,146 @@ struct smbios_type7 {
 	u8 eos[2];
 } __packed;
 
+/* System Slots - Slot Type */
+enum misc_slot_type {
+	SlotTypeOther = 0x01,
+	SlotTypeUnknown = 0x02,
+	SlotTypeIsa = 0x03,
+	SlotTypeMca = 0x04,
+	SlotTypeEisa = 0x05,
+	SlotTypePci = 0x06,
+	SlotTypePcmcia = 0x07,
+	SlotTypeVlVesa = 0x08,
+	SlotTypeProprietary = 0x09,
+	SlotTypeProcessorCardSlot = 0x0A,
+	SlotTypeProprietaryMemoryCardSlot = 0x0B,
+	SlotTypeIORiserCardSlot = 0x0C,
+	SlotTypeNuBus = 0x0D,
+	SlotTypePci66MhzCapable = 0x0E,
+	SlotTypeAgp = 0x0F,
+	SlotTypeApg2X = 0x10,
+	SlotTypeAgp4X = 0x11,
+	SlotTypePciX = 0x12,
+	SlotTypeAgp8X = 0x13,
+	SlotTypeM2Socket1_DP = 0x14,
+	SlotTypeM2Socket1_SD = 0x15,
+	SlotTypeM2Socket2 = 0x16,
+	SlotTypeM2Socket3 = 0x17,
+	SlotTypeMxmTypeI = 0x18,
+	SlotTypeMxmTypeII = 0x19,
+	SlotTypeMxmTypeIIIStandard = 0x1A,
+	SlotTypeMxmTypeIIIHe = 0x1B,
+	SlotTypeMxmTypeIV = 0x1C,
+	SlotTypeMxm30TypeA = 0x1D,
+	SlotTypeMxm30TypeB = 0x1E,
+	SlotTypePciExpressGen2Sff_8639 = 0x1F,
+	SlotTypePciExpressGen3Sff_8639 = 0x20,
+	SlotTypePciExpressMini52pinWithBSKO = 0x21,
+	SlotTypePciExpressMini52pinWithoutBSKO = 0x22,
+	SlotTypePciExpressMini76pin = 0x23,
+	SlotTypePC98C20 = 0xA0,
+	SlotTypePC98C24 = 0xA1,
+	SlotTypePC98E = 0xA2,
+	SlotTypePC98LocalBus = 0xA3,
+	SlotTypePC98Card = 0xA4,
+	SlotTypePciExpress = 0xA5,
+	SlotTypePciExpressX1 = 0xA6,
+	SlotTypePciExpressX2 = 0xA7,
+	SlotTypePciExpressX4 = 0xA8,
+	SlotTypePciExpressX8 = 0xA9,
+	SlotTypePciExpressX16 = 0xAA,
+	SlotTypePciExpressGen2 = 0xAB,
+	SlotTypePciExpressGen2X1 = 0xAC,
+	SlotTypePciExpressGen2X2 = 0xAD,
+	SlotTypePciExpressGen2X4 = 0xAE,
+	SlotTypePciExpressGen2X8 = 0xAF,
+	SlotTypePciExpressGen2X16 = 0xB0,
+	SlotTypePciExpressGen3 = 0xB1,
+	SlotTypePciExpressGen3X1 = 0xB2,
+	SlotTypePciExpressGen3X2 = 0xB3,
+	SlotTypePciExpressGen3X4 = 0xB4,
+	SlotTypePciExpressGen3X8 = 0xB5,
+	SlotTypePciExpressGen3X16 = 0xB6
+};
+
+/* System Slots - Slot Data Bus Width. */
+enum slot_data_bus_bandwidth {
+	SlotDataBusWidthOther = 0x01,
+	SlotDataBusWidthUnknown = 0x02,
+	SlotDataBusWidth8Bit = 0x03,
+	SlotDataBusWidth16Bit = 0x04,
+	SlotDataBusWidth32Bit = 0x05,
+	SlotDataBusWidth64Bit = 0x06,
+	SlotDataBusWidth128Bit = 0x07,
+	SlotDataBusWidth1X = 0x08,
+	SlotDataBusWidth2X = 0x09,
+	SlotDataBusWidth4X = 0x0A,
+	SlotDataBusWidth8X = 0x0B,
+	SlotDataBusWidth12X = 0x0C,
+	SlotDataBusWidth16X = 0x0D,
+	SlotDataBusWidth32X = 0x0E
+};
+
+/* System Slots - Current Usage. */
+enum misc_slot_usage {
+	SlotUsageOther        = 0x01,
+	SlotUsageUnknown      = 0x02,
+	SlotUsageAvailable    = 0x03,
+	SlotUsageInUse        = 0x04,
+	SlotUsageUnavailable  = 0x05
+};
+
+/* System Slots - Slot Length.*/
+enum misc_slot_length {
+	SlotLengthOther = 0x01,
+	SlotLengthUnknown = 0x02,
+	SlotLengthShort = 0x03,
+	SlotLengthLong = 0x04
+};
+
+/* System Slots - Slot Characteristics 1. */
+#define SMBIOS_SLOT_UNKNOWN		(1 << 0)
+#define SMBIOS_SLOT_5V			(1 << 1)
+#define SMBIOS_SLOT_3P3V		(1 << 2)
+#define SMBIOS_SLOT_SHARED		(1 << 3)
+#define SMBIOS_SLOT_PCCARD_16		(1 << 4)
+#define SMBIOS_SLOT_PCCARD_CARDBUS	(1 << 5)
+#define SMBIOS_SLOT_PCCARD_ZOOM		(1 << 6)
+#define SMBIOS_SLOT_PCCARD_MODEM_RING	(1 << 7)
+/* System Slots - Slot Characteristics 2. */
+#define SMBIOS_SLOT_PME		(1 << 0)
+#define SMBIOS_SLOT_HOTPLUG	(1 << 1)
+#define SMBIOS_SLOT_SMBUS	(1 << 2)
+#define SMBIOS_SLOT_BIFURCATION	(1 << 3)
+
+struct slot_peer_groups {
+	u16 peer_seg_num;
+	u8 peer_bus_num;
+	u8 peer_dev_fn_num;
+	u8 peer_data_bus_width;
+} __packed;
+
+struct smbios_type9 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 slot_designation;
+	u8 slot_type;
+	u8 slot_data_bus_width;
+	u8 current_usage;
+	u8 slot_length;
+	u16 slot_id;
+	u8 slot_characteristics_1;
+	u8 slot_characteristics_2;
+	u16 segment_group_number;
+	u8 bus_number;
+	u8 device_function_number;
+	u8 data_bus_width;
+	u8 peer_group_count;
+	struct slot_peer_groups peer[0];
+	u8 eos[2];
+} __packed;
+
 struct smbios_type11 {
 	u8 type;
 	u8 length;