This is (most of) the usb2 debug console code ripped out of

Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH] 
Rest of huge MCP55 patch).

I dropped a lot of stuff, like broken indenting, removed copyright messages,
and this printk_ram_* stuff (what the heck is this supposed to be)

This codebase is really a mess. Further tarball contributions without a
_CLEANED UP_ patch will be denied, especially if they are not from an up to
date svn tree.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 232 insertions, 0 deletions

diff --git a/src/include/ehci.h b/src/include/ehci.h
new file mode 100644
index 0000000000..ed54b7e347
--- /dev/null
+++ b/src/include/ehci.h
@@ -0,0 +1,132 @@
+#ifndef EHCI_H
+#define EHCI_H
+
+struct ehci_caps {
+        /* these fields are specified as 8 and 16 bit registers,
+         * but some hosts can't perform 8 or 16 bit PCI accesses.
+         */
+        u32             hc_capbase;
+#define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
+#define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
+        u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
+#define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
+#define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
+#define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
+#define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
+#define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
+#define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
+
+        u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
+#define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
+#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
+#define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
+#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
+        u8              portroute [8];   /* nibbles for routing - offset 0xC */
+} __attribute__ ((packed));
+
+/* Section 2.3 Host Controller Operational Registers */
+struct ehci_regs {
+
+        /* USBCMD: offset 0x00 */
+        u32             command;
+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
+#define CMD_PARK        (1<<11)         /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
+#define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
+#define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
+#define CMD_ASE         (1<<5)          /* async schedule enable */
+#define CMD_PSE         (1<<4)          /* periodic schedule enable */
+/* 3:2 is periodic frame list size */
+#define CMD_RESET       (1<<1)          /* reset HC not bus */
+#define CMD_RUN         (1<<0)          /* start/stop HC */
+
+        /* USBSTS: offset 0x04 */
+        u32             status;
+#define STS_ASS         (1<<15)         /* Async Schedule Status */
+#define STS_PSS         (1<<14)         /* Periodic Schedule Status */
+#define STS_RECL        (1<<13)         /* Reclamation */
+#define STS_HALT        (1<<12)         /* Not running (any reason) */
+/* some bits reserved */
+        /* these STS_* flags are also intr_enable bits (USBINTR) */
+#define STS_IAA         (1<<5)          /* Interrupted on async advance */
+#define STS_FATAL       (1<<4)          /* such as some PCI access errors */
+#define STS_FLR         (1<<3)          /* frame list rolled over */
+#define STS_PCD         (1<<2)          /* port change detect */
+#define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
+#define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
+
+        /* USBINTR: offset 0x08 */
+        u32             intr_enable;
+
+        /* FRINDEX: offset 0x0C */
+        u32             frame_index;    /* current microframe number */
+        /* CTRLDSSEGMENT: offset 0x10 */
+        u32             segment;        /* address bits 63:32 if needed */
+        /* PERIODICLISTBASE: offset 0x14 */
+        u32             frame_list;     /* points to periodic list */
+        /* ASYNCLISTADDR: offset 0x18 */
+        u32             async_next;     /* address of next async queue head */
+
+        u32             reserved [9];
+
+        /* CONFIGFLAG: offset 0x40 */
+        u32             configured_flag;
+#define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
+
+        /* PORTSC: offset 0x44 */
+        u32             port_status [0];        /* up to N_PORTS */
+/* 31:23 reserved */
+#define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
+#define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
+#define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
+/* 19:16 for port testing */
+#define PORT_LED_OFF    (0<<14)
+#define PORT_LED_AMBER  (1<<14)
+#define PORT_LED_GREEN  (2<<14)
+#define PORT_LED_MASK   (3<<14)
+#define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
+#define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
+/* 9 reserved */
+#define PORT_RESET      (1<<8)          /* reset port */
+#define PORT_SUSPEND    (1<<7)          /* suspend port */
+#define PORT_RESUME     (1<<6)          /* resume it */
+#define PORT_OCC        (1<<5)          /* over current change */
+#define PORT_OC         (1<<4)          /* over current active */
+#define PORT_PEC        (1<<3)          /* port enable change */
+#define PORT_PE         (1<<2)          /* port enable */
+#define PORT_CSC        (1<<1)          /* connect status change */
+#define PORT_CONNECT    (1<<0)          /* device connected */
+#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
+} __attribute__ ((packed));
+
+/* Appendix C, Debug port ... intended for use with special "debug devices"
+ * that can help if there's no serial console.  (nonstandard enumeration.)
+ */
+struct ehci_dbg_port {
+        u32     control;
+#define DBGP_OWNER      (1<<30)
+#define DBGP_ENABLED    (1<<28)
+#define DBGP_DONE       (1<<16)
+#define DBGP_INUSE      (1<<10)
+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
+#       define DBGP_ERR_BAD     1
+#       define DBGP_ERR_SIGNAL  2
+#define DBGP_ERROR      (1<<6)
+#define DBGP_GO         (1<<5)
+#define DBGP_OUT        (1<<4)
+#define DBGP_LEN(x)     (((x)>>0)&0x0f)
+        u32     pids;
+#define DBGP_PID_GET(x)         (((x)>>16)&0xff)
+#define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
+        u32     data03;
+        u32     data47;
+        u32     address;
+#define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
+} __attribute__ ((packed));
+
+#endif
diff --git a/src/include/usb_ch9.h b/src/include/usb_ch9.h
new file mode 100644
index 0000000000..13aa391cb3
--- /dev/null
+++ b/src/include/usb_ch9.h
@@ -0,0 +1,83 @@
+#ifndef USB_CH9_H
+#define USB_CH9_H
+
+#define USB_DIR_OUT                     0               /* to device */
+#define USB_DIR_IN                      0x80            /* to host */
+
+/*
+ * USB types, the second of three bRequestType fields
+ */
+#define USB_TYPE_MASK                   (0x03 << 5)
+#define USB_TYPE_STANDARD               (0x00 << 5)
+#define USB_TYPE_CLASS                  (0x01 << 5)
+#define USB_TYPE_VENDOR                 (0x02 << 5)
+#define USB_TYPE_RESERVED               (0x03 << 5)
+/*
+ * USB recipients, the third of three bRequestType fields
+ */
+#define USB_RECIP_MASK                  0x1f
+#define USB_RECIP_DEVICE                0x00
+#define USB_RECIP_INTERFACE             0x01
+#define USB_RECIP_ENDPOINT              0x02
+#define USB_RECIP_OTHER                 0x03
+/* From Wireless USB 1.0 */
+#define USB_RECIP_PORT                  0x04
+#define USB_RECIP_RPIPE                 0x05
+
+/*
+ * Standard requests, for the bRequest field of a SETUP packet.
+ *
+ * These are qualified by the bRequestType field, so that for example
+ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+ * by a GET_STATUS request.
+ */
+#define USB_REQ_GET_STATUS              0x00
+#define USB_REQ_CLEAR_FEATURE           0x01
+#define USB_REQ_SET_FEATURE             0x03
+#define USB_REQ_SET_ADDRESS             0x05
+#define USB_REQ_GET_DESCRIPTOR          0x06
+#define USB_REQ_SET_DESCRIPTOR          0x07
+#define USB_REQ_GET_CONFIGURATION       0x08
+#define USB_REQ_SET_CONFIGURATION       0x09
+#define USB_REQ_GET_INTERFACE           0x0A
+#define USB_REQ_SET_INTERFACE           0x0B
+#define USB_REQ_SYNCH_FRAME             0x0C
+
+#define USB_REQ_SET_ENCRYPTION          0x0D    /* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION          0x0E
+#define USB_REQ_RPIPE_ABORT             0x0E
+#define USB_REQ_SET_HANDSHAKE           0x0F
+#define USB_REQ_RPIPE_RESET             0x0F
+#define USB_REQ_GET_HANDSHAKE           0x10
+#define USB_REQ_SET_CONNECTION          0x11
+#define USB_REQ_SET_SECURITY_DATA       0x12
+#define USB_REQ_GET_SECURITY_DATA       0x13
+#define USB_REQ_SET_WUSB_DATA           0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE     0x15
+#define USB_REQ_LOOPBACK_DATA_READ      0x16
+#define USB_REQ_SET_INTERFACE_DS        0x17
+
+#define USB_DT_DEBUG                    0x0a
+
+#define USB_DEVICE_DEBUG_MODE           6       /* (special devices only) */
+
+//frim usb_ch9.h
+struct usb_ctrlrequest {
+        uint8_t bRequestType;
+        uint8_t bRequest;
+        uint16_t wValue;
+        uint16_t wIndex;
+        uint16_t wLength;
+} __attribute__ ((packed));
+
+struct usb_debug_descriptor {
+        uint8_t  bLength;
+        uint8_t  bDescriptorType;
+
+        /* bulk endpoints with 8 byte maxpacket */
+        uint8_t  bDebugInEndpoint;
+        uint8_t  bDebugOutEndpoint;
+};
+
+#endif
+
diff --git a/src/include/usbdebug_direct.h b/src/include/usbdebug_direct.h
new file mode 100644
index 0000000000..1790b1508e
--- /dev/null
+++ b/src/include/usbdebug_direct.h
@@ -0,0 +1,17 @@
+#ifndef USBDEBUG_DIRECT_H
+#define USBDEBUG_DIRECT_H
+
+struct ehci_debug_info {
+        void *ehci_caps;
+        void *ehci_regs;
+        void *ehci_debug;
+        unsigned devnum;
+        unsigned endpoint_out;
+        unsigned endpoint_in;
+};
+extern int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
+extern int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
+extern void set_ehci_base(unsigned ehci_base);
+extern void set_ehci_debug(unsigned ehci_deug);
+extern unsigned get_ehci_debug(void);
+#endif