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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-09 22:28:51 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-12 15:45:06 +0000 |
| commit | ced76f732f55f75356c9b65b1765b0a27d5ba442 (patch) | |
| tree | 9acf252e267327d6f6b905c2f85a42f4e6e2b06d /src/include | |
| parent | 7b6a397eec9893fc6d06952be23b1758fe4fd5a6 (diff) | |
include/cpu/x86/msr: fix MCG_CTL_P definition
MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of
that MSR contain the number of MCA banks being present on the CPU. At
the moment this definition of MCG_CTL_P is unused.
Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index ac48ca2de6..748aed5aa4 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -36,7 +36,7 @@ #define SMBASE_RO_MSR 0x98 #define IA32_SMM_MONITOR_VALID (1 << 0) #define IA32_MCG_CAP 0x179 -#define MCG_CTL_P (1 << 3) +#define MCG_CTL_P (1 << 8) #define MCA_BANKS_MASK 0xff #define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 |