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authorSugnan Prabhu S <sugnan.prabhu.s@intel.com>2021-08-31 07:19:30 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-02 22:55:00 +0000
commitcc50770cd0eeab0794264f2e6bccdfa7c117f2b9 (patch)
tree3ea6a55912fc299a472a8d7c3f0cd19d7708209c /src/include
parentd1fc832c527699265c7d04517010cc4b0ea6aabd (diff)
wifi: Add support for wifi time average SAR config
Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/sar.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/include/sar.h b/src/include/sar.h
index e8a1b287b5..f4ee0c5ac3 100644
--- a/src/include/sar.h
+++ b/src/include/sar.h
@@ -5,9 +5,10 @@
#include <stdint.h>
#define MAX_ANT_GAINS_REVISION 2
+#define MAX_DENYLIST_ENTRY 16
#define MAX_DSAR_SET_COUNT 3
#define MAX_GEO_OFFSET_REVISION 3
-#define MAX_PROFILE_COUNT 3
+#define MAX_PROFILE_COUNT 4
#define MAX_SAR_REVISION 2
#define REVISION_SIZE 1
#define SAR_REV0_CHAINS_COUNT 2
@@ -39,6 +40,13 @@ struct gain_profile {
uint8_t ppag_table[0];
} __packed;
+struct avg_profile {
+ uint8_t revision;
+ uint8_t tas_selection;
+ uint8_t tas_list_size;
+ uint8_t deny_list_entry[MAX_DENYLIST_ENTRY];
+} __packed;
+
struct sar_header {
char marker[SAR_STR_PREFIX_SIZE];
uint8_t version;
@@ -51,6 +59,7 @@ union wifi_sar_limits {
struct sar_profile *sar;
struct geo_profile *wgds;
struct gain_profile *ppag;
+ struct avg_profile *wtas;
};
void *profile[MAX_PROFILE_COUNT];
};