summaryrefslogtreecommitdiff
path: root/src/include
diff options
context:
space:
mode:
authorAndrey Petrov <andrey.petrov@intel.com>2016-07-15 13:31:09 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-19 20:20:13 +0200
commit64011880240cea5a3f8b1177853c7992a2d99ea8 (patch)
tree6f06cd735d182511d022d551d4a31d78185930a0 /src/include
parentfcd51ffae86752f2794e1e5998b84f7119b7f091 (diff)
soc/intel/common: Add reset_prepare() for common reset
Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/reset.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/include/reset.h b/src/include/reset.h
index 95ba608254..67f58db81f 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -10,5 +10,6 @@ void soft_reset(void);
void cpu_reset(void);
/* Some Intel SoCs use a special reset that is specific to SoC */
void global_reset(void);
-
+/* Some Intel SoCs may need to prepare/wait before reset */
+void reset_prepare(void);
#endif