summaryrefslogtreecommitdiff
path: root/src/include
diff options
context:
space:
mode:
authorYiwei Tang <tangyiwei.2022@bytedance.com>2023-06-05 16:38:23 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2023-06-28 09:03:59 +0000
commit51cfe49fd8e7a19a0e721bab005bb6f9b1016878 (patch)
tree0d9dc7b2f4c5d671be983528cc6d38300fc03916 /src/include
parenteaf44dc57aec53c567ff41ebb1b867b1b621e1a4 (diff)
mb/bytedance: Add 2 SPR sockets server board bd_egs
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids Scalable Processor chipset. It's utilising: - 2 SPR sockets - Max 32 DIMMs - 33x CPU PCIe slots - AST2600 for VGA and BMC remote management Test: The board boots to Linux 5.10 with all 192 cores available. All PCIe devices and DIMMS are working. # sudo dmesg --level alert,crit,err,warn [ 46.636896] netlink: 'consul': attribute type 1 has an invalid length. Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Co-authored-by: Jinfeng Li <lijinfeng01@ieisystem.com> Co-authored-by: Long Cao <caolong01@inspur.com> Co-authored-by: Hao Wang <wanghao11@inspur.com> Co-authored-by: Chenyu Lan <lanchenyu@inspur.com> Co-authored-by: Lay Kong <lay.kong@intel.com> Co-authored-by: Kehong Chen <kehong.chen@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Dong Wei <weidong.wd@bytedance.com> Co-authored-by: Chenchen Li <lichenchen.carl@bytedance.com> Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com> Reviewed-by: Haitao Nie <niehaitao@bytedance.com> Reviewed-by: Shijian Ge <geshijian@bytedance.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions