diff options
| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-12-26 05:16:47 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2010-12-26 05:16:47 +0000 |
| commit | 3344743215acab0b7805592a7c52a9c93636b347 (patch) | |
| tree | e1d6732a24920b319f7ca6c94fff1d0f9ede1b54 /src/include | |
| parent | 1c6d4e605588c03edf4e7ab70056d7c075fc5bb1 (diff) | |
Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index a75cb4710c..67fbc582cd 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -15,10 +15,15 @@ #define CPU_REV_2_2 0x022 #define CPU_REV_3_0 0x030 -/* GeodeLink Control Processor Registers, GLIU1, Port 3 */ -#define GLCP_CLK_DIS_DELAY 0x4c000008 -#define GLCP_PMCLKDISABLE 0x4c000009 -#define GLCP_CHIP_REVID 0x4c000017 +/* GeodeLink Control Processor Registers, GLIU1, Port 3 ; MSR_GLCP = 4c00xxxx */ +#define GLCP_CLK_DIS_DELAY (MSR_GLCP + 0x08) +#define GLCP_PMCLKDISABLE (MSR_GLCP + 0x09) +#define GLCP_DBGOUT (MSR_GLCP + 0x0C) +#define GLCP_PROCSTAT (MSR_GLCP + 0x0D) +#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16) +#define GLCP_CHIP_REVID (MSR_GLCP + 0x17) +#define GLCP_TH_OD (MSR_GLCP + 0x1E) +#define GLCP_FIFOCTL (MSR_GLCP + 0x5E) /* GLCP_SYS_RSTPLL, Upper 32 bits */ #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |