diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2024-08-10 11:29:56 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-11 13:40:07 +0000 |
| commit | 2b0459217546b0caa74665b80daadd49348fe7b7 (patch) | |
| tree | e387dbd5e8a951852752a162d0efd813e705d77e /src/include | |
| parent | b61114a6037c4999f61db9fe41f6783365db2486 (diff) | |
soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1
According to the Intel GPU list [1], these devices have the following
IDs:
8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] [2]
8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610]
8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] [3]
8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610]
Allows coreboot to correctly initialize IGD (8086:9ba8) in Intel Celeron
G5905 CPU (ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9).
This can also be verified using devicehunt.com [2,3].
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20240731150632/https://devicehunt.com/
view/type/pci/vendor/8086/device/9BA8
[3] https://web.archive.org/web/20230928015210/https://devicehunt.com/
view/type/pci/vendor/8086/device/9BA4
Change-Id: I776f434f3627d6fbd046a92eb736b1ffcac8274a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 24799b8826..43533a6e44 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4183,12 +4183,12 @@ #define PCI_DID_INTEL_CML_GT2_ULT_4 0x9B4C #define PCI_DID_INTEL_CML_GT1_ULX_1 0x9B20 #define PCI_DID_INTEL_CML_GT2_ULX_1 0x9B40 -#define PCI_DID_INTEL_CML_GT1_S_1 0x9B25 -#define PCI_DID_INTEL_CML_GT1_S_2 0x9B28 +#define PCI_DID_INTEL_CML_GT1_S_1 0x9BA5 +#define PCI_DID_INTEL_CML_GT1_S_2 0x9BA8 #define PCI_DID_INTEL_CML_GT2_S_1 0x9B45 #define PCI_DID_INTEL_CML_GT2_S_2 0x9B48 -#define PCI_DID_INTEL_CML_GT1_H_1 0x9B24 -#define PCI_DID_INTEL_CML_GT1_H_2 0x9B22 +#define PCI_DID_INTEL_CML_GT1_H_1 0x9BA4 +#define PCI_DID_INTEL_CML_GT1_H_2 0x9BA2 #define PCI_DID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DID_INTEL_CML_GT2_H_2 0x9B42 #define PCI_DID_INTEL_CML_GT2_S_G0 0x9BC8 |