diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2011-11-02 16:12:34 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-03-30 01:07:49 +0200 |
| commit | 00093a81d3f54c72215d9f402c3f88880da89a81 (patch) | |
| tree | 9e36867db1a94d195fdf69be11c3e847800ab82c /src/include | |
| parent | 1afe51af83ad0beb3f0ace1085524b327ecff7c6 (diff) | |
Add an option to keep the ROM cached after romstage
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/lapic.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 68608edab1..2215ec7ee5 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -27,8 +27,6 @@ static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void) do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY ); } - - static inline void enable_lapic(void) { @@ -53,7 +51,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } - +#ifndef __ROMCC__ #if CONFIG_AP_IN_SIPI_WAIT != 1 /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c @@ -156,4 +154,7 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ +int boot_cpu(void); +#endif + #endif /* CPU_X86_LAPIC_H */ |