diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-10-28 19:30:36 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-10 06:18:05 +0000 |
| commit | eaaa549e4a176637198f50570b81ecd3a7cf9549 (patch) | |
| tree | 0426227440ee1001999b18c612aad5f462b17d4d /src/include | |
| parent | 94fe086a067ad635246f40a339748182ef7b943e (diff) | |
cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers
It is too easy to confuse those with IA32_SMRR_PHYS_x registers.
Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 3bf8301cfd..b8d15179e9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,9 +31,10 @@ #define IA32_SMRR_PHYS_MASK 0x1f3 #define SMRR_PHYS_MASK_LOCK (1 << 10) -/* Specific to model_6fx and model_1067x */ -#define MSR_SMRR_PHYS_BASE 0xa0 -#define MSR_SMRR_PHYS_MASK 0xa1 +/* Specific to model_6fx and model_1067x. + These are named MSR_SMRR_PHYSBASE in the SDM. */ +#define CORE2_SMRR_PHYS_BASE 0xa0 +#define CORE2_SMRR_PHYS_MASK 0xa1 #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) |